1. Field of the Invention
This invention relates to a non-volatile, erasable and programmable interconnect cell, and more specifically to a self-sensing interconnect cell.
2. Description of Related Art
Typically, in the prior art, static random access memory (SRAM) cells have been used to programmably control transistor switches to interconnect input and output leads. However, the use of SRAM cells in programmable interconnects has numerous disadvantages. For example, an SRAM cell generally requires four to six transistors, thereby resulting in a relatively large interconnect cell. Additionally, an SRAM cell is volatile, i.e. the cell must be reprogrammed if the power goes off.
Hence, attempts have been made to design an interconnect cell which is non-volatile. For example, floating gate transistors themselves have been used to connect input and output leads. Although this configuration reduces the size of the interconnect cell, the programming characteristics of a floating gate transistor result in inherently low performance relative to a standard non-programmable transistor.
Another prior art configuration includes a floating gate transistor and a select transistor coupled to a sense amplifier. The sense amplifier is then connected to a pass transistor which interconnects input and output leads. The sense amplifier provides a high performance interconnect by ensuring an efficient switching of the pass transistor, but, because of its size, sacrifices cell density in the process.